The present invention generally relates to reset signal generating circuits, and more particularly to a reset signal generating circuit which generates a reset signal for resetting an internal logic circuit of a semiconductor device to an initial state when a power source is turned ON.
An internal circuit of a semiconductor device is reset after a power source is turned ON when applied with a power source voltage over a predetermined value, and starts an operation when the reset signal is cancelled. It is essential that such an internal circuit is applied with the reset signal for resetting the internal circuit to an initial state immediately after the power source is turned ON. For this reason, it is important that a reset signal generating circuit for generating the reset signal generates the required reset signal regardless of a speed with which the output power source voltage of the power source rises to the predetermined value.
FIG. 1 shows an example of a conventional reset signal generating circuit. The conventional reset signal generating circuit has a resistor 8 and a capacitor 9 connected in series between a power source voltage +Vs and the ground, and a reset signal is outputted from an output terminal 10 immediately after the power source is turned ON. The output terminal 10 connects to a node N between the resistor 8 and the capacitor 9.
When the power source is turned ON, the power source voltage +Vs rises toward a predetermined value. A speed with which the output power source voltage +Vs rises to the predetermined value will hereinafter be referred to as a rising speed. In a case where the rising speed is high, a terminal voltage (that is, the output reset signal) Vreset of the capacitor 9 rises with a charging time constant of the capacitor 9 as indicated by a phantom line I in FIG. 2(B) after the power source voltage +Vs shown in FIG. 2(A) reaches the predetermined value.
An internal circuit (not shown) connected to the output terminal 10 discriminates a low level when the voltage from the output terminal 10 is less than or equal to a predetermined threshold value and discriminates a high level when the voltage from the output terminal 10 is greater than the predetermined threshold value. Hence, when viewed from the side of the internal circuit, a binary signal indicated by a solid line II in FIG. 2(B) is obtained from the output terminal 10.
In a state where the power source voltage +Vs has reached the predetermined value, the voltage Vreset from the output terminal 10, that is, the input voltage Vreset of the internal circuit, indicates the reset signal when a logic level thereof is low and indicates a reset signal output prohibit state when the logic level thereof is high. In other words, the low level of the reset signal is active. Accordingly, in the conventional reset signal generating circuit, the reset signal is outputted normally during a time T shown in FIG. 2(B) when the rising speed of the power source voltage +Vs is high.
However, in a case where the rising speed of the power source voltage +Vs is low and it takes a long time for the power source voltage +Vs to reach the predetermined value from the time when the power source is turned ON as shown in FIG. 3(A), the charging of the capacitor 9 progresses by the time the power source voltage +Vs having the predetermined value is applied to the internal circuit. By the time the power source voltage +Vs reaches the predetermined value, the terminal voltage (that is, the output reset signal) Vreset of the capacitor 9 is either slightly greater than or slightly less than the threshold value of the internal circuit. Therefore, there are problems in that no low-level reset signal is outputted from the reset signal generating circuit in the former case shown in FIG. 3(B), and a time in which the low-level reset signal is generated is extremely short in the latter case.
Accordingly, in a semiconductor device having the conventional reset signal generating circuit for automatically resetting an internal circuit of the semiconductor device, it is essential that the power source voltage +Vs outputted from the power source rises to the predetermined value within a time which guarantees the generation of the active reset signal for a sufficiently long time to positively reset the internal circuit. Otherwise, it is necessary to generate an external reset signal and apply the reset signal to the internal circuit of the semiconductor device, but the use of such an external reset signal requires on the semiconductor device a terminal exclusively for receiving the external reset signal.
On the other hand, a reset signal generating circuit which generates an active reset signal only after the power source voltage +Vs reaches a reference voltage is disclosed in a Japanese Laid-Open Patent Application No. 61-288516. However, when there is a change in the power source voltage +Vs for some reason and the power source voltage +Vs ceases for a certain time, for example, there is a problem in that no active reset signal is generated when the power source voltage +Vs next rises to the reference voltage. In other words, no resetting of the internal circuit takes place even though the power source voltage +Vs once ceases.